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Ouput Stage

Terminology

  • THD: Total Harmonic Distortion

Class A

  • Power delivered to load (PL)
PL=VOrmsILrms=12VOp2RL
  • Power drawn from supply (PS)
PS=(P from M1)+(P from M2)=VDDID1+VSSID2=(VDD+VSS)I
note

consider the original definition of (AC) power

P=12π02πv(t)i(t)dt

in the PL case, we have the vary vO, thus we write

PL=12VpIpcos(θ)=VrmsIrms

however, in the PS case, we have an constant source VDD and VSS, thus

PS=12π02πVi(t)dt=V12π02πi(t)dt=VIavg

Class B

  • Power delivered to load (PL)

ignoring crossover distortion

PL=12VOp2RL
  • Power drawn from supply (PS)

for each MOS, only conducting in half period

PSn=PSp=VDDID=VDD12π02πVOpRLsinθdθ=VDDVOpπRL

and for total power

PS=PSp+PSn=2πVOpRLVDD
  • efficiency η
η=PLPS=π4VopVDD
  • dissipated power PD
PD=PSPL=2πVOpRLVDD12VOp2RL
  • PDmax w.r.t Vop
dPDdVo=2πVDDRLVoRL=0Vo=2πVDDPDmax=2PDnmax=2PDpmax=2VDD2π2RL

Class AB

CS Buffer

  • Output Resistance consider feedback (without RL) Rout
Routp=ro1+μgmpro1μgmpRoutn=ro1+μgmnro1μgmnRout=Routp||Routn=1μ(gmp+gmn)
  • Gain Error GE
GEvovivi=A1+A1=11+A1A=12μgmRL

Class D

  • Theoretically power-conversion efficiency is 100%
    since the input 1/0 pulse make transistors act as on-off switch, when the transistor on, there is no cross voltage, but current pass through. On the other hand, when transistor off, there is a large cross voltage but no current.

Power MOSFET

  • High Vt: 2V4V
  • In saturation region:
    • for low VGS:   iDVGS2
    • for high VGS:   iDVGS
      • (the velocity saturation is due to the saturation of mobility μ)

Temperature Effects

iD=12μCoxWL(VGSVt)2

for T μ, VT

  • for low VGS, TiD   (Δ[(VGSVt)2] dominates)

  • for high VGS, TiD   (Δ[μ] dominates)


Thermal Resistance

  • Junction temp. TJ
  • Ambient temp. TA
  • Thermal resistance between junction and ambience. θJA

  • Temperature here acts as voltage, and the dissipated power acts as current. Thus by Ohm's law we have

TJmaxTA=PDmaxθJA

Two Stage CMOS op-amp

Common-Mode

Acm12gm3RSSCMRR|Ad||Acm|=gm1(ro2||ro4)2gm3RSS

Input Common-Mode Range

  • lower limit (M1 leaving saturation, when VOV1=VDS1)
VICM+|Vtp|VD3=VSS+VGS3VICMVSS+VGS3|Vtp|
  • upper limit (M5 leaving saturation)
VDDVOV5VICM+VSG1VICMVDDVOV5VSG1

Output Swing

  • lower limit
vOVSS+VOV6
  • upper limit
vOVDDVOV7

PSRR

definition

PSRR+AdA+where A+vovddPSRRAdAwhere Avovss
  • PSRR+ :
    just remember that vO via second stage and vO via first stage would cancel out each other.

  • PSRR

    • vO from first stage is 0 (don't know fucking why)
    • vO from second stage is
vo=vssro7ro7+ro6PSRR=AdA=gm1(ro2||ro4)gm6(ro6||ro7)ro7ro7+ro6

Slew Rate

when |vid|>2VOV, the current would go through only one side of differential pair.

vo(t)=QCCC=ICCtSR=ICC=IGm1/ωt=IωtI/VOV=ωtVOV

Folded-Cascode CMOS op-amp

Input Common-Mode Range

  • upper limit (M1,M2 leave saturation)
VICMVtnVDDVOV9VICMVDDVOV9+Vtn
  • lower limit (M11 leaves saturation)
VICMVGS1VSS+VOV11VICMVSS+VOV11+VGS1

Output Swing

  • upper limit (M4 leaves saturation)
vOVDDVOV10VOV4
  • lower limit (M6 leaves saturation)
vOVSS+VGS7+VGS5Vtn6